The present invention relates generally to electrical circuits, and more particularly to a circuit and method of generating a hysteretic controller circuit having an increased natural frequency without requiring an alteration of the hysteresis window associated therewith.
Switching power supply circuits are utilized in a number of different circuit applications. The three basic switching power supply topologies in common use are the buck, boost and buck-boost type power stages. These topologies are non-isolated, that is, the input and output voltages share a common ground. There are, however, isolated derivations of these non-isolated topologies. The differing topologies refer to how the switches, output inductor and output capacitor associated therewith are interconnected. Each topology has unique properties which include the steady-state voltage conversion ratios, the nature of the input and output currents, and the character of the output voltage ripple. Another important property is the frequency response of the duty cycle-to-output voltage transfer function.
The most common power stage topology is the buck power stage, sometimes called a buck converter or a step-down power stage (because the output is always less than the input). The input current for a buck power stage is said to be discontinuous or pulsating if a switching current pulses from zero or some negative value to some positive output current value every switching cycle. The output current for a buck power stage is said to be continuous or nonpulsating because the output current is supplied by an output inductor/capacitor combination. In the latter event, the inductor current never reaches a zero or negative value.
An exemplary basic buck converter circuit is illustrated in prior art FIG. 1a, and designated at reference numeral 10. When a power switch 12 is activated, the switch behaves like a closed circuit, as illustrated in prior art FIG. 1b, and the input voltage VIN is applied to an inductor 14, and power is delivered to an output load 16. The output load voltage is VOUT=VINxe2x88x92VL, wherein the VL, the voltage across the inductor 14, is given by L(di/dt). The output voltage VOUT also is formed across a capacitor 18, thus the capacitor charges and the output voltage increases each time the switch 12 is closed.
When the switch 12 is deactivated, or turned off, the switch 12 behaves as an open circuit, as illustrated in prior art FIG. 1c, and the voltage across the inductor 14 reverses due to inductive flyback, thus making a circuit diode 20 forward biased. The circuit loop generated by the diode 20 allows the energy stored in the inductor 14 to be delivered to the output load 16, wherein the output current is smoothed by the capacitor 18. Typical waveforms for a buck converter are shown in FIG. 2. The power switch 12 is switched at a relatively high frequency (e.g., between about 20 KHz and about 300 KHz for most converters) to produce a chopped output voltage, however, the inductor 14 and capacitor 18 together operate as an LC filter to produce a relatively smooth output voltage having a DC component with a small ripple voltage overlying the DC value (see, e.g., output voltage waveform of FIG. 2). The ripple voltage can be controlled by varying the duty cycle of the power switch control voltage.
The base principle of operation in the above buck converter 10 is often utilized in hysteretic dc-dc converters, as illustrated in prior art FIG. 3, and designated at reference numeral 30. The circuit 30 is similar in various respects to the buck converter 10 of FIG. 1a and employs a unity gain buffer 32 serially coupled to an analog comparator circuit 34 having a hysteresis VH. The comparator 34 compares the input reference voltage VREF to the circuit output voltage VOUT and provides an output signal at node 36 which is a function of the comparison and constitutes a generally square wave. An exemplary output voltage waveform for the circuit 30 is illustrated in FIG. 4. The hysteresis VH of the comparator 34 impacts the operation of the circuit 30 in the following manner. As the output VOUT falls below a voltage VREFxe2x88x92VH, the comparator 34 trips and the output thereof at node 36 goes from zero to the supply, ideally, which then is fed to the circuit output VOUT (wherein, VOUT is a function of the output of the comparator and the duty cycle of the driver). Similarly, as VOUT increases to a voltage VOUT+VH, the comparator 34 again trips and the output thereof at node 36 decreases to zero volts, which is fed to the circuit output VOUT. Therefore the hysteresis VH of the comparator 34 dictates an amount of voltage ripple (2*VH) about the target reference voltage VREF, as illustrated in FIG. 4, and, in conjunction with the output capacitor dictates a natural frequency of the ripple voltage at the output VOUT.
In many applications it is desirable to increase the natural frequency of the circuit 30 since a higher frequency allows use of a smaller capacitor, provides a smaller output ripple voltage, and provides a faster circuit response time. One conventional way of decreasing the natural frequency of a hysteretic dc-dc converter is to decrease the hysteretic window of the comparator 34. That is, instead of using a hysteretic value of VH, a smaller value (e.g., VHxe2x88x92xcex94VH) is used. With a smaller hysteretic window, the comparator 34 trips earlier, thus increasing the natural frequency. While decreasing the hysteretic window in systems employing relatively large ripple voltages (e.g., on the order of about 100 mV or more) is a viable solution, such an approach is not practical in systems employing smaller ripple voltages (e.g., on the order of about 50 mV or less) because in such systems it becomes difficult to generate a well-controlled hysteresis window that is small and simultaneously insensitive to noise and random offset voltages. In other words, the accuracy requirements of the hysteretic comparator are generally more stringent for lower ripple voltages.
Therefore there is a need in the art for a circuit and method of providing an increased natural frequency in hysteretic circuits without altering the hysteretic window associated therewith.
According to the present invention, a circuit and method of increasing the natural frequency of a hysteretic circuit without altering the hysteretic window associated therewith is disclosed. Additionally, the invention is conducive to being easily integrated within an integrated circuit solution and is easily realizable in CMOS or BiCMOS type fabrication processes.
The present invention increases the natural frequency of a hysteretic dc-dc converter circuit without altering the signal-to-noise ratio of the defining hysteresis window. The present invention generates and couples an AC ramp signal to the input reference voltage. The AC ramp signal preferably is an inverted version of the feedback output voltage used as the sense node in conventional circuit. The AC ramp signal is utilized as an additional feedback mechanism and, together with the conventional sense node feedback, is used to generate a natural frequency which is greater than conventional circuits without requiring a modification of the hysteresis within the converter.
The AC ramp signal preferably maintains the duty cycle information of the converter circuit to assure proper operation. The duty cycle information is retained by utilizing the input voltage VIN, which then is used to generate the ramp signal.
According to one aspect of the present invention, a hysteretic dc-dc converter circuit includes a feedback circuit in addition to the traditional feedback for generating a natural frequency that is greater than conventional circuits. The feedback circuit includes a level shifter circuit which generates an inverted signal with respect to the comparator output which contains the duty cycle information associated with the converter, and derives an inverted ramp signal associated therewith. The derived inverted ramp signal is superimposed over the input reference voltage and used with the output voltage to drive a hysteretic comparator circuit. Because the inputs are out of phase, the comparator is tripped more frequently despite no required change in the comparator hysteresis. The increased comparator trip frequency results in an increase in the natural frequency of the converter.
According to another aspect of the present invention, a method of increasing a natural frequency of a hysteretic dc-dc converter is disclosed. The method comprises initiating the operation of a buck converter circuit and feeding back an output signal of the buck converter circuit to a comparator circuit. A feedback ramp signal is then generated, which is out of phase with the output signal, and the feedback ramp signal is fed to the comparator circuit. The comparator circuit then generates an output signal based on the converter output signal and the generated feedback ramp signal, wherein the comparator circuit output signal exhibits an increased natural frequency without requiring an alteration of the hysteretic window of the comparator circuit.
To the accomplishment of the foregoing and related ends, the invention, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed and the present invention is intended to include all such embodiments and their equivalents. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.